1. Field of Invention
The present invention relates to a shift register that is used for driving an electro-optical panel having scan lines, data lines, pixel electrodes and switching devices which are arranged in a matrix so as to correspond to the intersections of the lines, and also to a data-line driving circuit and a scan-line driving circuit which use the shift register.
2. Description of Related Art
Conventional driving circuits in electro-optical devices, such as liquid crystal devices, have a data-line driving circuit, a scan-line driving circuit, and the like for supplying, respectively, data-line signals, scan-line signals, and the like to data lines, scan lines, and the like at predetermined timings.
The basic configuration of the data-line driving circuit varies depending on whether an input image signal is analog or digital. In either case, however, the data-line driving circuit has a shift register for sequentially shifting a transfer signal initially supplied in a horizontal scanning period, in response to a clock signal.
Japanese Unexamined Patent Application Publication No. 10-199284 discloses such a shift register, and FIG. 13 illustrates the circuit thereof. The shift register has serially-connected basic units, each being driven by a clock signal HCK and an inverted clock signal HCKX, which is inverted from the clock signal HCK. In this case, a basic unit Un at an nth stage has inverters INV1, INV2, and INV3, a NOR circuit, and switches SWa and SWb. The switches SWa and SWb are turned on when control voltages are at a low level and are turned off when they are at a high level. The inverters INV1 and INV2 invert respective input signals and output the resulting signals when the control voltages are at a high level, and sets the respective output terminals into a high impedance state when the control voltages are at a low level.
With such a circuit, it is not required that the inverters INV1 and INV2 operate constantly, but is sufficient if they operate during a period of time only when a signal Dn or a signal Dn+1 is active. Thus, the NOR circuit NOR determines the inverted OR of the signals Dn and Dn+1 and controls the switches SWa and SWb in accordance with the determined result. Consequently, the clock signal HCK and the inverted clock signal HCKX are supplied to the inverters INV1 and INV2 in only a predetermined period of time.
It is, therefore, possible to limit a period of time when the clock signal HCK and the inverted clock signal HCKX are supplied to the individual basic units constituting the shift register. Consequently, it is possible to reduce the power consumption of the shift register.